This invention relates to a method for autoaligning overlapped lines of a conductive material in electronic circuits integrated on a semiconductor substrate.
Electronic EPROM or Flash EPROM memory devices integrated on a semiconductor substrate include a plurality of non-volatile memory cells arranged in a matrix form; that is, the cells are laid into rows, or word lines, and columns, or bit lines.
Each non-volatile memory cell includes an MOS transistor whose gate electrode, located above the channel region, is floating, that is, has a high D.C. impedance to all the other terminals of the cell and the circuit in which the cell is connected.
The cell also has a second electrode, called the control gate, which is coupled to the gate electrode and is driven by means of appropriate control voltages. The other transistor electrodes include the usual drain and source terminals.
In recent years, considerable effort has gone to the development of memory devices with ever higher circuit density. This effort has resulted in electrically programmable, contactless non-volatile memory matrices with a cross-point type of structure becoming available. An example of a matrix of this kind, and of its manufacturing process, is described in European Patent No. 0 573 728 to this Applicant, and hereby incorporated by reference.
In matrices of this type, the matrix bit lines are formed in the substrate as continuous parallel diffused strips. Following the formation of the gate regions of the matrix cells, the memory matrix appears as a series of posts (projecting elements) projecting from the semiconductor surface. At this stage, after filling the gaps which separate the various gate regions with a dielectric, the word lines of the memory matrix are formed which must be aligned to the gate regions of the cells appearing at the same row in the memory matrix.
The operation for defining and aligning a polysilicon line, such as that representing a word line of a memory matrix, to a previously defined polysilicon layer underneath is critical because their dimensions are comparable.
If a misalignment occurs in defining the upper word line, the underlying layer, which is usually made of the same material as the upper layer, is most likely to be etched away or damaged.
There exists a physical limitation to the alignment of material layers belonging to successive lithographic levels. This limitation applies most strictly to the manufacturing of memory cell matrices, where the geometrical dimensions are carried to the lower limit of the photolithographic process.
Shown in FIG. 1 is a portion 1xe2x80x2 of a matrix of memory cells wherein the gate regions 2xe2x80x2 of the memory cells have been formed.
Following the deposition of a fill layer 4xe2x80x2, from which the gate regions 2xe2x80x2 of the matrix will project, the polysilicon lines WL"" are formed which are to be aligned to the gate regions 2xe2x80x2.
In conformity with well-established designing rules, to collimate, or to correctly fix the lines WL"" to their corresponding gate regions, a variation X is allowed which is set by the photolithographic limitations.
Accordingly, it has become common practice to form the upper line with a width which exceeds by at least 2xc3x97 the width of the underlying portion.
However, this solution has some drawbacks. Where the distance between two adjacent lines is exceedingly small and each line is made oversize, the lines may ultimately be too close together.
On the other hand, where the line WL"" formed in the upper layer is the same width as the lower line, the underlying gate regions may suffer damage in the event of a photolithographic misalignment occurring during the definition of the line WL"", as highlighted by FIG. 1.
In this case, it would become necessary to collimate the upper line to the line underneath.
Until now, there exists no method to align overlapped polysilicon lines, which allows the lines of conductive material to be collimated, removes the need for forming oversize lines, and overcomes the limitations with which prior methods are still beset.
Embodiments of this invention provide spacers on the line to which the upper line must be collimated, so as to increase the space available on the underlying line, instead of forming an oversize upper line.
A method is provided that autoaligns lines of a conductive material by first forming projecting regions on a semiconductor substrate, forming a fill layer in the gaps between the regions, and then planarizing the fill layer to expose a portion of the regions. Portions of the regions are etched, forming voids compared to the fill layer. These voids are filled with an insulating layer, then partially etched, at the center of the top surface of the regions only, which leaves an insulating structure at the top periphery of the regions.
The features and advantages of a device according to the invention will become apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. The invention relates, particularly but not exclusively, to a method for autoaligning the word lines of non-volatile memory matrices, and the description which follows will cover this field of application for convenience of illustration.